Register Map Generator

Describe your control/status registers in YAML. Get a synthesizable APB4 SystemVerilog register block, a self-checking testbench, a C header and Markdown documentation. Everything runs in your browser: your spec never leaves your machine.

How it works

Write your register map in YAML, or click Visual editor to build it graphically: drag registers around the address map, and drag across bits to create, move and resize fields.
Check the Preview tab for bit-field layout, overlaps and gaps.
Download the RTL, testbench, header and docs. All are generated from the same spec, so they always agree.
Run the testbench (iverilog -g2012 or verilator --binary) to check the generated block before you integrate it.

Spec reference

Key	Where	Meaning
`name`	top	Block name. The module is `<name>_regs`.
`data_width`	top	8, 16, 32 (default) or 64.
`addr_width`	top	Width of `paddr`. Optional; the minimum that fits the highest offset is used if omitted.
`slverr_on_unmapped`	top	Assert `pslverr` on accesses to unmapped offsets (default `true`).
`offset`	register	Byte offset, aligned to the data width. Optional: defaults to the next word after the previous register.
`fields`	register	List of bit fields. Omit it and give `access`/`reset` on the register for one full-width field.
`strobe`	register	Add `<reg>_wr_o` / `<reg>_rd_o` one-cycle pulses (e.g. for FIFO push/pop).
`bits`	field	A single bit (`3`) or range (`"15:8"`). Quote ranges.
`access`	field	One of the access types below.
`reset`	field	Reset value (decimal, `0x…`, `0b…`). Quote values above 2⁵³.

Access types and hardware ports

Access	Software	Hardware ports	Notes
`rw`	read / write	`_o` value	Byte strobes respected.
`ro`	read	`_i` value	No storage; reads sample the input directly.
`wo`	write, reads 0	`_o` value
`w1c`	read, write 1 to clear	`_o` value, `_set_i`	Hardware set wins over a same-cycle software clear, so events are never lost.
`w1s`	read, write 1 to set	`_o` value, `_clr_i`	Software set wins over a same-cycle hardware clear.
`rc`	read, clears on read	`_o` value, `_set_i`	The read returns the value before clearing; a same-cycle hardware set wins.

Generated bus interface

The block is an AMBA APB4 completer with zero wait states (pready tied high), asynchronous active-low reset (presetn), and pstrb byte-lane write masking. Low address bits below the word size are ignored. prdata is driven combinationally from the address during the access phase.

FAQ

Is the output synthesizable?

Yes. It uses plain always_ff/always_comb SystemVerilog with no vendor primitives.

Is my spec uploaded anywhere?

No. Generation runs in JavaScript in your browser. "Share link" encodes the spec into the URL fragment, which browsers don't send to the server.

What about AXI4-Lite, UVM RAL, SystemRDL or IP-XACT?

These are planned. Tell us which you need most.