About LatchedUp

Free, accurate tools for the everyday chores of hardware design, built by a hardware engineer.

Who builds it

I'm an electrical and computer engineer who has worked on hardware, PCB design, and digital ASIC and SoC integration. LatchedUp collects the tools I kept wishing existed: small, fast and correct, with no install, sign-up or licence server.

How the tools are built

• Private by design. Everything runs in your browser. Your register maps and specs never leave your machine.
• Verified, not just generated. Generated RTL is simulated with Icarus Verilog and Verilator, lint-checked, and tested against deliberately injected bugs before a tool is released.
• Free. The site may carry a few unobtrusive ads or sponsors to cover costs. The tools stay free.

Tools

• Register map generator: YAML → APB4 SystemVerilog, self-checking testbench, C header and docs.
• CRC/LFSR generator: coming next.

Contact

Bug reports, feature requests and sponsorship enquiries: hello@latchedup.com. If a tool produced something wrong, send the spec that triggered it and I'll fix it.